Since the SM5842 can only receive signal with maximum Fs at around 48kHz, it is not possible for D1V3 and D1V33 to receive 96k signal. Due to that I have find one solution to do that using a AD1896 (or SRC4192) ASRC below.
DIR9001 –> AD1896 + 11.2896MHz XO –> SM5842 –> PCM63.
With above configuration, the input Fs can be from 32k till 96k while the output Fs from AD1896 is fixed at 44.1kHz. AD1896 is set to Async mode with slave input mode and master output mode. Both AD1896 and SM5842 is using master clock from the XO at 11.2896MHz. Thus the jitter at SM5842 XTI will 100% depend on the quality of the XO.
Of course I can use a XO frequency of 12.288MHz to have a ouput Fs at 48kHz but I do not have this XO frequency on hand. With higher Fs and later 8x over sample in the SM5842, the output noise after Jfet IV with single pole filter will be minimized.
Here is the picture of my implementation:
